The controller provides the constellation data and status information to the MATLAB host by using UDP blocks. The model displays status information such as number of frames synchronized, estimated CFO, decoded header information (modType and codeRate), number of header and data CRC pass and failures, number of bits received, and number of bit errors from the OFDM receiver. The periodic task drives the control and status signals of the hardware algorithm through the AXI4-Lite registers. The periodic task is a timer-driven task with a periodic time of 1e-2, which is defined in the task manager. The processor logic contains a read task and a periodic task. The Vector Interpolation block interpolates the input samples by 8 (491.52 MSPS) and sends them to the RF Data Converter block as a vector of eight samples. In the transmit path, the OFDM Transmitter block sends the samples to the RF Data Converter block through the Vector Interpolation block. The OFDM Receiver block sends the processed data to the processor with a sample time of 61.44 MHz. The sample rate after the Vector Decimator block is 61.44 MSPS, as expected by the OFDM TxRx subsystem for its processing. The Vector Decimator block decimates input vector samples by 8 and sends them to the OFDM receiver. In the receive path, the Vector Decimator block receives the packed eight samples with a sample rate of 491.52 MSPS from the RF Data Converter block. The Select Payload Data subsystem contains an LUT that stores the data bits used for transmitter waveform generation. With these settings, the Stream clock frequency parameter is 3932.16/(8*8) = 61.44 MHz. Similarly, in the DAC tab, set the Interpolation mode (xN) parameter to 8 and the Samples per clock cycle parameter to 8. To get the clock cycle (baseband sample rate) to 61.44 MSPS, set the Samples per clock cycle parameter to 8. The effective sample rate after decimation is 491.52 MSPS. Set the Decimation mode (xN) parameter to 8. This value is calculated and displayed on the block mask as the Stream clock frequency (MHz) parameter after you click Apply. For this example, the desired value is 61.44 MSPS. Choose the values of Interpolation mode (xN), Decimation mode (xN), and Samples per clock cycle parameters such that the effective clock cycle (sample rate) for the wireless algorithm FPGA is the desirable value. Set the NCO frequency parameter for the DAC and ADC mixers to 0.860 GHz, and set the DAC and ADC sample rate to 3932.16 MSPS. To meet the 860 MHz RF carrier frequency and 61.44 MSPS baseband sample rate, configure the RF Data Converter block according to the settings described here and shown in the figure. The block provides an interface to the Xilinx RF Data Converter IP in Simulink to model a wireless system destined for implementation on a Xilinx RFSoC device.
To configure the analog to digital converter (ADC) and digital to analog converter (DAC) settings, use the RF Data Converter block. An RFSoC device has its RF data converter connected to the PL.
0 kommentar(er)
